General Information
| HOT CHIPS 3 (1991) | |
|---|---|
| Date | August 26-27, 1991 |
| Place | Memorial Hall Auditorium, Stanford University |
| Program | Final Program  |
| Committees | Organizing and Program Committees |
Conference Day One
| Session | Monday, August 26, 1991 |
|---|---|
| Opening Remarks 098:30-8:45 |
General Chair: Martin Freeman Program Co-Chairs: Forest Baskett, John Hennessey |
| Session 1 08:45-10:15 |
High Performance Processors – I Chair: John Hennessey, Stanford UniversitySuperSPARCTM : A Fully Integrated Superscalar Processor, Greg Blanck, Sun Microsystems, Steve Krueger, Texas Instruments.
MlPS R4000 Technical Overview, Earl Killian, MlPS Computer Systems PA-RISC Processor for “Snakes” Workstation, Charles Kohlhardt, Hewlett Packard |
| Session 2 10:45-12:15 |
Highly Parallal Chips Chair: Martin Freeman, Philips Research The LIFE Family of High-Performance Single Chip VLlWs, Gerrit Slavenburg and Yen Lee, Philips Research Palo Alto Andrew Huang, CMU
The Message-Driven Processor, William Dally, J. Stuart Fiske, Waldemar Horwat, John Keen, Richard Lethin, Michael Noakes and Peter Nuth MIT Artificial Intelligence Laboratory The TRW CPUAX Superchip, A. Miscione, R. Almeida, H. Hennecke and R. Mann TRW Electronics and Technology Division |
| Session 3 1:45-3:15 |
High-Performance Processors – 2 Chair: Forest Baskett, Silicon GraphicsAn 80 MHz 64-Bit Floating Point RISC Processor with Direct DRAM Support, James Hesson, Micron Technology
The i860TM XP: 2nd Generation of the i860TM Beyond Claims of Free Transistors and Abundant Instruction-Level Parallelism , Michael Smith, Stanford University |
| Session 4 3:45-5:15 |
Low Power and Low Cost Chair: Alan Smith, U.C. BerkeleyTera microCORE Chipset, Greg Favor, Tera Microsystems
The SparKITTM Chipset, Mohammed Wadi, LSI Logic Corporation SPARCore Modules, Raju Vegesna, Ross Technology |
| 7:30 | Evening Panel Session Five Instructions Per Clock: Truth or Consequences Session Chairs: Alan Smith, U.C. Berkeley and John Mashey, MlPS Computer Systems Panelists: Joseph A Fisher, Hewlett Packard Laboratories; Norm Jouppi, DEC Western Research Lab; Monica Lam, Stanford University; James Smith, Cray Research; David Wall, DEC Western Research Lab |
Conference Day Two
| Session | Tuesday, August 27, 1991 |
|---|---|
| Session 5 09:00-10:30 |
HigCommunications Chair: Teresa Meng, Stanford University A GaAs 200 Mbps 64×64 Crosspoint Chip, Ron Cates, Vitesse Semiconductor An Enhanced Crossbar Router Chip for a Shared Memory The NEURON Chip Family Architecture, Robert Dolin, Echelon The Protocol Engine Chipset, Des Young, Protocol Engines |
| Session 6 11:00 -12:30 |
Caches and Floating Point Chair: John Crawford, IntelMlPS R4000 Caches and Coherency, Paul Ries, MlPS Computer Systems
The Megacell Differentiated Floating Point Product Family, Merrick Darley, Don Steiss, Peter Groves, David Bural 82495DX/82490DX: A High-Performance 2nd Level Cache |
| Session 7 2:00-3:30 |
Special Processors Chair: John Mashey, MlPS Computer System A Smart Frame Buffer, Joel McCormack, DEC Western Research Laboratory Bob McNamara and Lindsay Gage, DEC |
| Session 8 4:00-5:00 |
High-Performance Processors – 3 Chair: Dave Ditzel, Sun MicrosystemsNational’s Swordfish – A Superscalar with DSP, Reuven Marko and Motti Beck, National Semiconductor T9000 – Superscalar Transputer, Bob Krysiak, Richard Forsyth and Roger Shepherd INMOS Ltd. – SGS-Thomson Microelectronics |
| 5:00 | Closing Remarks |